As described in an article entitled "Integrated Switched-Capacitor Low-Pass Filter with Combined Anti-Aliasing Decimation Filter for Low Frequencies", IEEE J. Solid-State Circuits, vol. SC-17, PP. 1024-1028 (12/82), by D. C. von Grunigen et al., a SC filter operates as a sampled-data network. As a result, the input signal must be band limited to prevent aliasing. A technique presented by von Grunigen et al. uses a SC prefilter (referred to as a decimation filter) that provides zeros at integer multiples of a clock frequency f.sub.c. This is accomplished by sampling the SC prefilter at a higher clock rate nf.sub.c. FIG. 3 of this article shows such an SC prefilter.
One of a number of uses for a SC filter is in a baseband signalling circuit of a cellular telephone.
One problem that arises in the use of a cellular telephone is when it is desired to employ two different signalling protocols, such as a wide bandwidth signalling protocol and a narrow bandwidth signalling protocol.
For example, one wide bandwidth voice channel protocol is known as Advanced Mobile Phone Service (AMPS). AMPS is used in parts of North and South America. Another wide bandwidth voice channel protocol is known as Total Access Communication System (TACS), which is used in, by example, the United Kingdom, Italy, and Spain. Two Narrow bandwidth voice channel protocols are known as NAMPS and NTACS, both of which employ subaudible signalling.
Difficulties arise in that the NAMPS/NTACS signalling protocols are quite different from that of the AMPS/TACS signalling protocols. The most significant differences include the following.
In AMPS/TACS the signalling is a "blank-and-burst" type; i.e., the voice signal is muted during signalling. However, in the NAMPS/NTACS system the signalling is accomplished by continuous subaudible signalling below the voice band. As a result, in NAMPS/NTACS the voice signal acts as an interference signal for the subaudible signalling.
The effective bit rate for the signalling circuit is 10 Kbit/s and 8 Kbit/s for AMPS and TACS, respectively, but only 100 bit/s for NAMPS/NTACS.
The deviation for signalling is .+-.8 Khz/.+-.6.4 Khz in AMPS/TACS, and .+-.700 Hz in NAMPS/NTACS. If it is desired to maintain the same demodulation sensitivity of the RF receiver for both protocols, a problem arises in that the input signal level of the signalling circuit will be reduced by the same ratio in NAMPS/NTACS, as compared to AMPS/TACS.
Furthermore, when employing the NAMPS/NTACS protocols the interfering voice signal must be attenuated during signalling data reception.
One method of solving this problem is to employ the SC technique described by von Grunigen et al. to convert the effective input sampling frequency to a higher frequency in order to ease the anti-aliasing filtering requirements.
A main function of an analog front end of the signalling circuit, in addition to filtering noise and interference, is to detect the zero crossings of the incoming data signal by converting the signal to a square wave signal to be used in subsequent digital data processing circuitry. In this process, the difference between the DC level of the signal at the input to comparator and a DC comparison level becomes critical. Thus, any additional DC voltage added to the signal distorts the detection of the zero crossings of the input data signal, resulting in an increase in the Bit Error Rate (BER) of the detected subaudible signalling data.
One major source of this DC level shift is the offset voltages of the operational amplifiers (opamps) in the signal filters. In that a significant amount of amplification is required, due to the low input signal levels (nominally 35 mVpp for NAMPS); with conventional circuit structures the offset voltages of the opamps are also amplified. As a result, the DC offset of the signal is increased, leading to the above described difficulties in extracting the signalling data.
A straightforward solution to this problem is to provide a DC blocking capacitor and a DC biasing resistor at the input of the data comparator. However, the corner frequency of the DC blocking components must be very low (less than 2 Hz) when operating with the NAMPS/NTACS protocols, due to the low signalling frequency. This would require a large RC constant, which is extremely difficult or impossible to provide within a typical integrated circuit structure. One solution would be to implement the DC blocking function with external components. However, this approach would require additional interface pins for the integrated circuit. Furthermore, the use of external components would increase both the total cost and the area required for a printed circuit board.
In an article entitled "Improved Offset-Compensation Schemes For Switched-Capacitor Circuits", (ISCAS '84), pages 1054-1057, by K. Haug et al., techniques are described for compensating offset voltages of the opamps in SC circuits. FIG. 2 of this article shows an offset-free non-inverting SC integrator wherein an input-referred DC offset voltage of an operational amplifier is cancelled during the period (phi 1=1). This phase should thus be used for sampling by a subsequent stage. Eq. 5 describes a change in the output voltage during the period (phi 2=1), compared to the period (phi 1=1), and shows that the change is small, and that the opamp slew requirements are relaxed (FIG. 5). Although the opamp offset is totally compensated, this article describes an integrator, and not a decimator.
An article entitled "Spike-Free Switched-Capacitor Circuits", Electronics Letters 9th, Vol. 23 No. 8, (4/87), pages 428-429, by H. Matsumoto et al., describes an improvement to these structures, and shows the use of capacitance multiplier (CM) feedback.